1. Field of the Invention
This invention relates to a multiprocessor circuit provided with a plurality of CPUs, and particularly relates to a multiprocessor circuit intended for improvement of throughput by controlling input of interruption (interrupt) signals to each CPU.
2. Description of the Prior Art
A conventional multiprocessor circuit provided with a plurality of CPUs has its CPUs connected in parallel in relation to the interruption signal line for inputting interruption signals. It receives interruption signals input from the interruption line with one of the CPUs for processing.
In such a multiprocessor circuit with the configuration described above, there is no clear rule for distribution of interruption signals among CPUs. Therefore, a particular CPU sometimes receives a much larger number of interruption signals and is placed under much heavier load than others.
This prolongs the processing time of such a CPU and results in lower throughput of the whole multiprocessor circuit.